The resolution limit of lithography is typically limited by the wavelength of the light used and the numerical aperture of the illumination system used. The following holds true: a=k·λ/NA, where k is the coherence factor of the radiation having the wavelength λ and NA designates the numerical aperture. To fulfill specific technological requirements, it is necessary in some applications in semiconductor technology and fabrication to produce very small structures, in particular even the smallest possible structures, which have to far surpass the resolution capability of lithography.
Lithography methods employed at the present time use excimer lasers as a light source, for example ArF lasers having a wavelength of 193 nm or KrF lasers having a wavelength of 248 nm. In this case, it is possible to achieve a maximum resolution of approximately 65 nm, i.e., the minimum size or dimension that can be produced or the minimum spacing that can be produced for structures is about 65 nm.
There are areas of application in which structures having a smaller size or dimension than 65 nm are particularly desirable.
Semiconductor memory cells such as, for example, PRAMs or PCRAMs include phase change materials. Phase change random access memories are non-volatile memories that exploit the properties of a phase change material whose electrical resistance changes greatly in accordance with its crystalline phase. Examples of phase change materials of this type are chalcogenides, i.e., compounds or alloys of the elements of group VI of the periodic table. By heating a phase change material and allowing it to cool down in accordance with a predetermined temperature profile, the phase of the phase change material is altered to a crystalline or amorphous state, thereby producing a characteristic resistance value in each case. The associated temperature profile is caused by impressing a corresponding current profile.
By way of example, a memory cell in the amorphous state is programmed by heating the phase change material to a temperature lying between the crystallization temperature and the melting point, and maintaining this temperature long enough (approximately 50 ns) to obtain a crystalline state having a low resistance value. This is realized by applying a current pulse having a suitable amplitude and a corresponding duration. Conversely, during an erasure operation, the phase change material is heated to a temperature lying somewhat above the melting point of the phase change material by applying a relatively high current pulse for a short time duration. The phase change material is subsequently cooled rapidly. As a result, the phase change material layer is altered in such a way that it is present in an amorphous phase having a high resistance value. In the case of the phase change materials that are usually used, the resistance values of the respective phases differ by in each case approximately 100 fold, so that the presence of a specific phase can be unambiguously identified by measuring the resistance value.
In order to realize a desired phase change from amorphous to crystalline or from crystalline to amorphous with a smallest possible impressed current, great current concentration (i.e., generation of a high current density) is necessary. The known PCRAMs are primarily realized as so-called heater cells, in which a buried metal contact makes contact with the active phase change material deposited in planar fashion, see for example “OUM—A 180 nm Nonvolatile Memory Cell Element Technology for Stand alone and embedded Applications” by Stefan Lai and Tyler Lowrey, IEDM Tech. Dig. 2001, page 36.5. In this case, a high current density can be obtained by a reduced conductor cross-section of the metal contact and, in particular, by using a sub-lithographic metal contact.
FIG. 8 shows a schematic cross-section through the memory node of a memory cell having phase change material (PCRAM). A second electrode 20 is arranged on the top side of a layer made of a phase change material such as, for example, a polycrystalline chalcogenide. A heater or an electrical contact 21 is locally connected to a volume 23 of the layer made of the phase change material 22 that is to be programmed. The conductive layer is connected to a first electrode 19 at the other side. If a current then flows between the first and second electrodes 19, 20, the region 23 is locally heated and thus transferred from a crystalline to an amorphous state, or vice versa.
A metal contact having a sub-lithographic dimension can be realized via a spacer process, for example. First, a spacer layer, for example made of SiO2, is deposited conformally in a suitable layer thickness d. The horizontal part of the spacer layer is subsequently removed by an anisotropic etching. As a consequence, the cross-section of the associated contact opening is reduced by the size 2×d. Afterward, a layer made of a conductive material, for example a titanium nitride layer, is deposited via a CVD method and planarized using a CMP (chemical mechanical polishing) method.
This technique is associated with the problem that it is nevertheless not possible to realize arbitrarily small dimensions of the metal contacts. Moreover, it is necessary to deposit the spacer layer conformally, which is usually effected via a CVD method. Since high temperatures are possibly required for a conformal layer deposition, this gives rise to the disadvantage, however, that the thermal budget of the component is burdened by this step.
The production of Si quantum wires having a width of less than 30 nm via a spacer process is disclosed in Jaewoo Kyung, “Fabrication of sub-30 nm nanowires”, School of Electrical Engineering, Seoul Nat. Univ., SMDL Annual report 2002.
A further disadvantage of producing structures using the spacer technique results from the fact that it is not possible to produce such contacts with particularly small spacings of less than, for example, the minimum size that can be obtained lithographically.
Further PCRAM memory cell concepts are disclosed in U.S. Pat. No. 6,740,921 and U.S. Patent Application Publication No. U.S. 2004/0164290.